10Gig E took almost 10 years from the time the standard was ratified till it was deployed in large quantities within campuses, data centers and for WAN aggregation. What are the driving applications/business needs for 40G/100G Ethernet? And when will we see line rate multi-port switches as commercial products?
The biggest market for 40G Ethernet is in data centers. The 100G Ethernet is more for core network aggregation of 10G and 40G Ethernet links. Ithin the data center, the main competition for 40G E is Infiniband. By comparison, higher-speed Ethernet will capitalize on the large installed base of Gigabit (and 10G) Ethernet. New 40G and 100G products will become less expensive and more available over time, and will be supported by many silicon and equipment vendors. The Ethernet standard also is universally understood by data center network administrators, so the relative costs for managing and troubleshooting Ethernet are much lower than for a niche fabric such as Infiniband.
We will explore these issues and many others at the Oct 13 IEEE ComSocSCV meeting “40/100 Gigabit Ethernet – Market needs, Applications, and Standards.” There will be 3 presentations followed by a panel session to be moderated by ComSocSCV officer Prasanta De. Here is a summary of the talks:
1. Ethernet’s Next Evolution – 40GbE and 100GbE by John D’Ambrosia
This talk will provide an overview of the Ethernet Eco-system and the applications within that drove the need for the development of IEEE Std. 802.3baTM-2010 40Gb/s and 100Gb/s Ethernet Standard. Technology trends in computing and network aggregation and their role in driving the market need for 40GbE and 100GbE will be discussed.
2. The IEEE Std 802.3ba-2010 40Gb/s and 100Gb/s Architecture by Ilango Ganga
This session provides an overview of IEEE Std 802.3ba-2010 40Gb/s and 100Gb/s Ethernet specifications, objectives, architecture and interfaces.
The next generation higher speed Ethernet addresses the needs of computing, aggregation and core networking applications with dual data rates of 40Gb/s and 100 Gb/s. The 40/100 Gigabit Ethernet (GbE) architecture allows flexibility, scalability and leverages existing 10 Gigabit standards and technology where possible. The IEEE Std 802.3ba-2010 provides physical layer specifications for Ethernet communication across copper backplane, copper cabling, single-mode and multi-mode optical cabling systems.
The 40/100 Gigabit Ethernet utilizes the IEEE 802.3 Media Access Control sublayer (MAC) coupled to a family of 40 and 100 Gigabit physical layer devices (PHY). The layered architecture includes multilane physical coding sublayer (PCS), physical medium attachment sublayer (PMA) and physical medium dependant sublayers (PMD) for interfacing to various physical media. It also includes an Auto-Negotiation sublayer (AN) and an optional forward error correction sublayer (FEC) for backplane and copper cabling PHYs. The optional management data input/output interface (MDIO) is used for connection between 40/100 GbE physical layer devices and station management entities. The architecture includes optional 40 and 100 Gigabit Media Independent Interfaces (XLGMII and CGMII) to provide a logical interconnection between the MAC and the Physical Layer entities. It includes 40 and 100 Gigabit attachment unit interfaces (XLAUI and CAUI), four or ten lane interface, intended for use in chip-to-chip or chip-to-module applications. It also includes a 40 and 100 Gigabit parallel physical interface (XLPPI and CPPI), four or ten lane non-retimed interface, intended for use in chip-to-module applications with certain optical PHYs. The presentation will also outline the applications for some of the above interfaces.
3. Physical Layer (PCS/PMA) Overview by Mark Gustlin, Principal Engineer, Cisco Systems
This paper describes the Physical Coding Sublayer (PCS) and the Physical Medium Attachment (PMA) for the 40-Gb/s and 100-Gb/s Ethernet interfaces currently under standardization within the IEEE 802.3ba task force. Both of these speeds will initially be realized with a parallel PMD approach which requires bonding multiple lanes together through a striping methodology. The PCS protocol has the following attributes: Re-uses the 10GBASE-R PCS (64B/66B encoding and scrambling), just running at 4x or 10x as fast to provide for all of the required PCS functions for the data which will traverse multiple PMD lanes. Part of the PCS is a striping protocol which stripes the data to the PMD lanes on a per 66 bit block basis in a round robin fashion. Periodically an alignment block is added to each PMD lane. This alignment block acts as a marker which allows the receive side to deskew all lanes in order to compensate for any differential delay that the individual PMD lanes experience. The PMA sublayer provides the following functions: Provides per input-lane clock and data recovery, bit level multiplexing to change the number of lanes, clock generation, signal drivers and optionally provides loopbacks and test pattern generation/checking.
Presentations are posted at 2010 Meeting archives (top left) of www.comsocscv.org
Please see numerous comments which update the market status.