Infineon PSoC MCUs Expand TinyML into a Broader Range of Edge AI Applications
Disclaimer: ChatGPT helped research and write this article.
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Introduction:
Artificial intelligence (AI) running on embedded devices is evolving beyond the relatively narrow range of machine-learning applications traditionally associated with TinyML [1.], rather than Large Language Models (LLMs). Newer microcontrollers (MCUs) are beginning to support a broader class of Edge AI workloads, including speech recognition, natural-language processing, computer vision, optical character recognition (OCR), selected translation applications and increasingly sophisticated voice interfaces. Many selected AI workloads can now be executed locally on embedded MCUs, reducing or eliminating the need for cloud processing for those particular functions.
Note 1. Traditional TinyML (Tiny Machine Learning) focuses on relatively small, task-specific machine-learning models running on resource-constrained embedded devices. The newer development is the ability to supplement those workloads with compact language models and more sophisticated speech and vision inference.
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Infineon’s PSoC™ Edge family of microcontrollers illustrates this transition. By combining heterogeneous Arm processors, dedicated neural-network accelerators, substantial memory resources, graphics capabilities and embedded AI software, these MCUs provide a platform for intelligent devices capable of performing more complex AI processing locally.
Infineon states: “The relevant question is not whether an MCU can replicate an 8B LLM, but whether it can deliver useful AI experiences within the power, cost, and latency constraints of edge products. For many real-world edge applications, PSOC™ Edge is not merely capable, it is often a more appropriate solution than a higher-(processing) power MPU-based architecture.”
Let’s examine that assertion and consider Edge AI applications that can be supported by the Infineon PSoC MCUs.
Edge AI Applications supported by Infineon PSoC MCUs:
Infineon’s PSoC Edge MCUs support TinyML, which consists of low-latency, deterministic AI models that process sensor, audio, and vision data locally. The hardware is designed for applications requiring battery-powered execution, sub-1 milliwatt wake states, and zero cloud dependency.
From Infineon: PSoC Edge AI Applications include:
Audio & Voice Processing:
- Speech-to-Intent: Converting spoken commands directly into system actions (e.g., “Turn on the fan”) without needing to transcribe speech into text first.
- Acoustic Event Detection: Identifying specific environmental sounds such as glass breaking, baby crying, gunshots, or alarms.
- Beamforming & Noise Reduction: Using neural networks to filter out background noise in communication devices and smart wearables.
Low-Power Vision (TinyVision):
- Presence & Gesture Detection: Recognizing if a human is in front of a device or interpreting basic hand movements for touchless control.
- Object & Face Counting: Tracking things like people entering a room or basic inventory sorting on a conveyor belt.
- Defect Classification: Performing basic visual quality inspections in automated manufacturing lines.
Smart Sensing & Predictive Maintenance:
- Vibration and Anomaly Detection: Monitoring industrial motors, pumps, or consumer appliances to predict mechanical failure before it happens.
- Sensor Fusion: Combining data from multiple sensors (e.g., temperature, pressure, humidity, and gas sensors) to evaluate environmental conditions or air quality index (AQI) changes in real time.
- Biometric Tracking: Processing health metrics locally in fitness trackers, such as advanced heart-rate variability and sleep stage classification.
The table below illustrates how the PSoC Edge E84 matches these workloads by splitting tasks between its distinct processing domains:
| Workload Type | Active Hardware Component | Typical Power/Performance State |
| Always-On Passive Listening | Cortex-M33 + NNLite microNPU | Ultra-low power, sub-1 mW state waiting for wake words or threshold anomalies. |
| Active Machine Learning Inference | Cortex-M55 + Arm Ethos-U55 NPU | High performance, using 128 MACs/cycle execution to compute vision or audio matrices instantly. |
Source: Infineon
Infineon PSOC Edge MCUs bring more capable AI processing to embedded devices, supporting applications ranging from speech recognition and compact language models to computer vision and intelligent human-machine interfaces. Image generated by ChatGPT.
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PSoC Edge: A Heterogeneous Architecture for Embedded AI:
The PSoC Edge family is designed to combine high-performance AI inference with low-power, always-on processing. Its multi-domain architecture enables different processors and neural accelerators to handle workloads according to their performance and power requirements.
The PSOC Edge E84, used in the EWNA demonstration, incorporates:
- Arm Cortex-M55: A 400 MHz processor with Helium DSP extensions for signal processing and machine-learning workloads.
- Arm Ethos-U55-128 NPU: A dedicated neural processing unit for accelerating neural-network inference.
- Arm Cortex-M33: A separate, lower-power processor operating at up to 200 MHz.
- Infineon NNLite: A dedicated neural-network accelerator associated with the Cortex-M33 domain for low-power, always-on AI applications.
The E84 also provides up to 6 MB of system SRAM, 512 KB of resistive RAM (RRAM), external-memory interfaces and a low-power 2.5D graphics processor. Its display controller supports MIPI-DSI/DBI interfaces and resolutions up to 1024 × 768. Multiple digital audio interfaces support multi-microphone applications, including far-field voice interaction. Connectivity includes USB, 10/100 Ethernet, CAN-FD, SPI, UART, I2C, I3C and I2S.
This heterogeneous architecture provides two important processing domains:
- High-performance domain: The Cortex-M55 and Ethos-U55 combination handles more computationally demanding AI workloads, including full voice inference and more complex neural-network applications.
- Low-power domain: The Cortex-M33 and NNLite combination supports continuous, energy-efficient processing, including wake-word detection and other always-on machine-learning functions.
This arrangement is particularly useful for intelligent voice interfaces. The lower-power domain can monitor for an activation phrase without requiring the higher-performance processing resources to remain continuously active. Once activated, more demanding speech-recognition and language-model workloads can use the higher-performance domain.
The result is a flexible MCU architecture that combines conventional embedded processing with multiple levels of AI acceleration.
PSOC Edge family: Different configurations for different AI workloads:
Not all PSOC Edge devices offer identical AI and HMI capabilities. Infineon’s product comparison identifies the following differences:
| MCU | AI acceleration | Voice AI | Vision AI | Graphics |
|---|---|---|---|---|
| E84 | NNLite + Ethos-U55-128 | Full voice inference | Presence, gesture, motion | Yes |
| E83 | NNLite + Ethos-U55-128 | Full voice inference | Presence, gesture, motion | No |
| E82 | NNLite | Wake-word detection | Not listed | Yes |
| E81 | NNLite | Wake-word detection | Not listed | No |
Source: Infineon data sheets
The E84 offers the broadest combination of the capabilities listed above, including full voice inference, vision functions and graphics. This differentiation is important when evaluating the family for embedded AI designs. The appropriate MCU depends on the workload, processing requirements, Human Machine Interface (HMI) complexity, memory resources and power budget.
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Infineon Demo At Embedded World North America (EWNA) 2026:
At EWNA 2026 [September 22–24, 2026 in Anaheim CA], Infineon demonstrated an on-device Edge AI application using the PSOC™ Edge E84. The demonstration integrated a 6.5-million-parameter Nexus Ember task-oriented language model, with a 512-token context window, and a 16-million-parameter FastConformer streaming speech-to-text engine, together with graphics support. The application demonstrated local speech recognition and language-model inference without requiring cloud processing for those functions.
Of particular interest, Infineon supplied detailed measurements of the implementation, including model size, memory utilization, language-model generation speed, speech-recognition latency and power consumption. These provide useful engineering data for evaluating the feasibility of executing compact language models and multiple AI workloads on MCU-class hardware.
Its reported measurements—18 generated tokens per second, a 0.36-second language-model time to first token, approximately 17 MB peak memory usage for the 16M voice-control pipeline excluding graphics buffers, and 92.6 mW active SoC power—provide useful evidence of what is achievable with a compact MCU-based AI implementation.
The broader application opportunities include advanced speech recognition, interactive voice interfaces, task-oriented language models, selected translation workloads, computer vision, gesture recognition, OCR and industrial monitoring.
These MCUs will not replace application processors (see Addendum below), embedded Linux systems or cloud-based AI infrastructure for large language models and computationally intensive multimodal applications. Their significance is different: an expanding range of useful AI functions can now be performed locally on increasingly capable microcontroller platforms. For embedded-system designers, that can mean reduced dependence on cloud services, improved data privacy, lower communication requirements, faster interaction and potentially lower system cost and power consumption.
Paradigm Shift: Why Localized AI Execution Matters (Source: Google Gemini):
- Deterministic Latency & Reliability: By removing reliance on cellular, Wi-Fi, or cloud backends, critical applications suffer zero network dropouts (1:14). Latency drops to a deterministic sub-second window, which is vital for industrial machinery interfaces or responsive consumer electronics (0:11).
- Ironclad Data Privacy: Because processing happens entirely on the local silicon chip, sensitive voice data, visual captures, and text streams never leave the device boundary (0:25). This inherently complies with privacy frameworks and eliminates consumer data exposure risks.
- Drastic Power Savings: Transitioning an RF radio into high-throughput transmit mode to stream audio or video payload data to the cloud consumes significant energy. Offloading neural processing locally to a highly optimized NPU cuts total system energy consumption drastically, extending battery life and making “always-on” edge devices sustainable
Conclusions:
The important development is that Edge AI is no longer limited to narrowly defined TinyML inference. Infineon’s PSOC Edge family demonstrates how microcontrollers can increasingly support intelligent, voice-enabled, vision-aware and language-model-driven embedded applications.
The combination of heterogeneous processing, neural-network acceleration, graphics and memory resources enables a broader range of applications, including conversational interfaces, speech recognition, computer vision, OCR, selected translation workloads and industrial monitoring. The E84 demonstration provides concrete evidence that compact language models and streaming speech recognition can operate together locally, with relatively low power consumption.
Although MCU-based Edge AI will not replace more powerful application processors or cloud-based AI for demanding workloads, it can reduce cloud dependence, improve privacy and responsiveness, and lower system costs for many embedded applications. The opportunity is to bring useful AI capabilities directly into devices that traditionally relied on much simpler embedded processing.
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Addendum:
Google Gemini suggests using dedicated Application Processors (MPUs) or Edge Accelerators for open ended AI at the edge.
To support more demanding, general-purpose generative AI at the edge applications than the Infineon PSoC Edge MCUs, designers will typically need to move beyond MCU architectures to application processors (MPUs) or dedicated AI accelerators with substantially greater memory capacity and bandwidth. Microcontrollers lack the extreme memory bandwidth and capacity (such as High Bandwidth Memory or large external LPDDR buses) required to execute unconstrained, open-ended generative text and vision models.
| Processor Category | Example Hardware | Generative AI Capabilities |
|---|---|---|
| High-End Edge NPU Modules | NVIDIA Jetson Orin Nano / NX | Runs 1B to 3B parameter models locally with fast token generation. Uses shared unified LPDDR5 VRAM to fit small LLMs (e.g., Llama 3.2 3B or Qwen 2.5 3B) entirely on the device. |
| Application Processors | NXP i.MX 95 / STMicroelectronics STM32MP2 | Can handle highly optimized, tiny text models or text-to-speech tasks, but constrained by memory bandwidth. Ideal for structured, deterministic multi-modal smart interfaces rather than open-ended text gen. |
| Dedicated AI Accelerators | Hailo-8 / Raspberry Pi AI Kit | Excellent for offloading complex vision and neural network computations if paired with a capable host CPU. Designed for highly power-efficient mathematical processing (up to 26 TOPS) but lacks on-chip external DRAM for massive LLM weight pools. |
| Product | Official vendor hyperlink |
|---|---|
| NVIDIA Jetson Orin Nano / NX | NVIDIA Jetson Modules |
| NXP i.MX 95 | NXP i.MX 95 Applications Processor |
| STMicroelectronics STM32MP2 | STMicroelectronics STM32MP2 Series |
| Hailo-8 | Hailo AI Products |
| Raspberry Pi AI Kit | Raspberry Pi AI Kit |
Note: The original Raspberry Pi AI Kit uses the Hailo-8L (13 TOPS), not the Hailo-8 (26 TOPS) in the first “Overview of Edge AI Hardware Tiers.. Raspberry Pi’s official documentation confirms this distinction.
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Architectural Deep Dive: Why These Distinctions Matter:
The Memory Wall Constraint: Single-stream token generation for language models is heavily throttled by memory bandwidth rather than raw TOPS compute. This is why High-End NPU Modules with high-throughput unified memory architectures excel at localized LLM tasks over general-purpose application processors.
Coprocessor Offloading: Dedicated accelerators like the Hailo-8 require a powerful host CPU (like an ARM Cortex-A) because the accelerator manages the parallelized weight matrices for neural layers while the host handles system OS routines, memory routing, and basic context token tracking.
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References:
https://www.infineon.com/products/microcontroller/32-bit-psoc-arm-cortex/32-bit-psoc-edge-arm
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From ChatGPT following our discussion of the Google Gemini Addendum:
The Expanding Edge AI Computing Continuum:
The Infineon PSOC Edge demonstration illustrates that the choice of Edge AI hardware is increasingly determined by the application workload, rather than simply by the size or theoretical performance of the AI processor. MCU-based platforms are attractive for applications requiring low power consumption, deterministic response, local data processing and relatively compact, task-oriented AI models. More demanding applications involving larger language models, longer context windows, complex multimodal inference or higher sustained throughput will generally require more capable application processors or dedicated accelerators with greater memory capacity and bandwidth.
Importantly, these hardware categories are complementary rather than directly interchangeable. A dedicated vision accelerator, for example, is not automatically suitable for general-purpose LLM inference. Developers should evaluate actual application performance, including inference latency, sustained token generation, model accuracy, memory utilization and energy consumption per task. The ultimate objective is to select the most appropriate processing architecture for the required Edge AI experience, not simply the processor with the highest TOPS rating.