2026 OCP Summit: Full-Stack AI Networking Silicon from Nvidia/Cisco and Broadcom; Ethernet vs InfiniBand Interconnects
Executive Summary:
At the 2026 Open Compute Project (OCP) Global Summit in San Jose, CA this week, the multi-vendor push for open, gigawatt-scale AI networks reached a critical tipping point as Cisco and Broadcom deployed massive 102.4 Tbps Ethernet fabrics to challenge Nvidia’s proprietary grip. These and other networking silicon companies are responding to what Cisco executives call a new “Network Supercycle” triggered by agentic AI workloads. The architectural battle lines for gigawatt-scale AI infrastructure were drawn between open ecosystems and proprietary stacks. Broadcom championed the open alternative by introducing its 102.4 Tbps Tomahawk 6 switching platform and third-generation TH6-Davisson Co-Packaged Optics (CPO) to drastically reduce power consumption across clusters exceeding 100,000 accelerators.
- Cisco accelerated this so called “Network Supercycle” by highlighting massive hyperscaler traction for its custom Silicon One P200 routing chips, which Microsoft and Alibaba Cloud have integrated into their custom architectures to handle dense, geographically distributed AI workloads.
- Nvidia defended its market dominance with its Quantum-3 InfiniBand switches and native sub-2µs point-to-point latency; however, despite InfiniBand technically originating as an open industry standard, Nvidia’s sole manufacturing monopoly, closed software integration with CUDA, and proprietary extensions like SHARP have effectively turned it into a vertically locked, high-premium ecosystem. This strict architectural division has forced hyperscalers to choose between the seamless, turnkey acceleration of Nvidia’s proprietary pipeline for tight scale-up GPU environments, or the superior multi-vendor economics, flexibility, and anti-lock-in guardrails offered by Broadcom and Cisco’s open Ethernet frameworks.
- Broadcom launched an open Ethernet fabric architecture designed for gigawatt-scale clusters scaling past 100,000 parallel AI accelerators, showcasing innovations like the 102.4 Tbps Tomahawk 6 and Jericho 4 silicon. The company also introduced TH6-Davisson Co-Packaged Optics, Thor Ultra 800G NICs, and Open Rack Version 3 blueprints to compete with proprietary InfiniBand stacks. You can read more about Broadcom’s announcements at the official corporate site.
I. Cisco has worked with Nvidia on an Ultra-Dense Small Form-Factor Pluggable (USFP), a transceiver that conforms to the Octal Small Form-Factor Pluggable (OSFP) footprint that governs most high-speed datacenter transceivers today. Cisco said USFP enables the industry to accelerate AI by building on the ecosystem models that have powered today’s AI networks. By combining a path to higher-capacity fabrics and improved efficiency with familiar operational practices, USFP helps customers scale AI infrastructure while maintaining the flexibility, interoperability, and consistency required at scale.
Unlike other optical transceivers, the leading versions of which are designed to handle 200-Gb/s today, USFP provides 400-Gb/s full-duplex data rates over 16 lanes with 32 in the future, achieving transmission rates from 6.4 Tb/s up to 12.8 Tb/s. Nvidia said scalability is facilitated by an internal connector technology that reduces wear and improves signal integrity. USFP works with switches and SmartNICs. The new USFP is designed to save power without requiring liquid cooling, something that other solutions feature—most notably Arista Network’s eXtra-dense Pluggable Optics (XPO) solution, which packs its own liquid-cooled cold plate.
Cisco and NVIDIA claim that, compared to an OSFP module supporting 200-Gb/s, the new USFP has approximately 1.3X the power efficiency. At the same time, the USFP matches the footprint of today’s OSFP transceivers, making for an easier transition than the new form-factor XPO, which Arista says improves density by a factor of 4X. The two companies said they’ll work with a “community-led multi-source project” to create an open industry specification for USFP. Members of that “community” were not identified. 
Source: NVIDIA and Cisco
In a blogpost, Cisco executives Bill Gartner, SVP and GM, Optical Systems and Optics, and Will Eatherton, SVP Networking Engineering, stated:
“To help customers scale AI infrastructure efficiently and sustainably, Cisco takes a full-stack, co-designed platform approach that combines silicon, high-density systems, optics, software, and operational expertise. USFP reflects that philosophy. Rather than a standalone innovation, it is part of a broader platform vision that advances scale, efficiency, and performance while preserving the deployment, serviceability, and lifecycle models customers depend on.”
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Cisco also highlighted massive cloud traction for its custom Silicon One P200 routing chip, which provides 51.2 Tb/s of high-buffering switching capacity designed to seamlessly link vast, geographically distributed AI data sites. Microsoft and Alibaba Cloud.
“As our infrastructure demands grow, the P200’s robust architecture provides the speed and enhanced buffering capabilities necessary to address the increasing scale of our cloud and high-performance services,” said Anand Ramakrishna, Corporate Vice President, Engineering, Microsoft, in a statement.
Alibaba has embedded the Silicon One P200 into its Quantum Cat router. “We paired Cisco’s silicon with Alibaba’s custom systems and the SONiC operating system,” stated Dennis Cai, Vice President, Head of Network Infrastructure, Alibaba Cloud Intelligence Group. “This combination … delivers the flexibility and operational power required for some of the world’s most demanding networks.”
Cisco also said that its previously announced 102.4-Tb/s Silicon One G300 is now available for customer sampling, with some G300-powered systems shipping to customers. Another chip, the 51.2-Gb/s G302, is designed to function at top-of-rack (ToR) deployments for scale up or scale across infrastructure.
Cisco’s OCP announcements indicate the networking market leader’s efforts to continue unifying its full-stack strategy around its own silicon, switching, and software, a tack that so far has proved successful.
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- Tomahawk 6 & Jericho 4 Silicon: Broadcom demonstrated live partner systems running its 102.4 Tbps Tomahawk 6 switching platform for low-latency frontend fabrics, alongside Jericho 4 silicon for deep-buffered scale-out routing.
- TH6-Davisson Co-Packaged Optics (CPO): This third-generation CPO architecture integrates optics directly onto the switch substrate. By eliminating internal copper traces to traditional transceivers, it drastically reduces power consumption per gigabit.
- Thor Ultra 800G NICs: These high-performance network interface cards support line-rate 800 Gbps RoCE (RDMA over Converged Ethernet) throughput, accelerating memory-to-memory data transfers while bypassing CPU overhead.
- ORV3 Ecosystem Blueprint: Broadcom aligned its PCIe Gen 6 switches, retimers, and optical components with the Open Rack Version 3 (ORV3) and Open Rack Wide standards, supporting dense liquid-cooled rack configurations.
- Open Standard Commitments: Under standardizing frameworks like ESUN (Ethernet for Scale-Up Networking), Broadcom pitched open Ethernet as the primary economic and physical alternative to proprietary InfiniBand fabrics for frontier AI clusters.
- Enterprise LAN and Client-to-Server Interconnects: Connects standard server racks to local networks, user devices, and the broader internet.
- Front-End Data Center Networks: Manages standard cloud computing workloads, database queries, and multi-tenant hosting environments.
- Emerging AI Backends (via RoCEv2): Through frameworks like the Ultra Ethernet Consortium (UEC) and platforms like NVIDIA’s Spectrum-X, modern 800Gbps Ethernet is increasingly deployed by hyperscalers (such as Meta and xAI) for AI clusters due to its superior Total Cost of Ownership (TCO) and rapid innovation cycle.
- Ecosystem and TCO: Leverages a massive global supply chain and existing IT skills, avoiding the proprietary premium and single-vendor lock-in common with InfiniBand.
- RoCE Adaptability: Uses RDMA over Converged Ethernet (RoCEv2) along with Priority Flow Control (PFC) to emulate the low-latency, lossless advantages of InfiniBand over traditional network lines.
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- Header Optimization: Standard Ethernet headers carry massive protocol overhead that increases latency for small data frames. ESUN implements a streamlined, compact 4-byte ESUN Header (EH) to maximize packet efficiency, strip away unneeded bytes, and drastically lower transport latency.
- Lossless Reliability & Tail Latency Control: AI workloads depend heavily on synchronized “collective” mathematical operations where a single dropped packet can stall the entire training run. ESUN implements advanced Credit-Based Flow-Control (CBFC) to guarantee zero packet loss and tightly manage jitter and tail latency.
- Decoupled Multi-Vendor Interoperability: ESUN focuses strictly on how network switches and network interface cards (NICs) handle frame formatting and packet switching. By keeping the fabric protocol-agnostic, it allows accelerators to define their own host-side transport layers independently, allowing operators to mix-and-match silicon suppliers.
| Networking Initiative | Governing Body | Primary Focus | Role in the AI Ecosystem |
|---|---|---|---|
| ESUN | Open Compute Project (OCP) | Scale-Up Network Fabric (L2/L3 switching and framing) | Optimizes the actual network switches and packet formatting inside the physical rack. |
| SUE-T (Scale-Up Ethernet Transport) | Open Compute Project (OCP) | Scale-Up Endpoint Transport (XPU-to-XPU communication) | A specialized transport protocol layer designed to work natively inside the ESUN switch framework to handle load balancing and transaction scheduling. |
| UEC (Ultra Ethernet Consortium) | Linux Foundation | Data Center-Wide Networks (Initially Scale-Out, expanding to Scale-Up) | A broader, top-to-bottom architecture that ESUN actively pulls specifications and best practices from to align with global standards. |
III. Ethernet vs. InfiniBand for Interconnects:
The structural battle between Broadcom’s open Ethernet platform and Nvidia’s proprietary InfiniBand fabric [1.] are direct competitors for backend compute & storage interconnects in data centers, high-performance computing (HPC), and AI clusters within data centers. The technical architectures, advantages, and philosophies of both approaches contrast sharply.
Note 1. InfiniBand by itself is an open, industry-standard specification managed by the InfiniBand Trade Association (IBTA). Nvidia acquired its primary architect, the Israeli company Mellanox, for $6.9 billion in 2019. However, in the context of modern AI data centers, Nvidia has effectively turned InfiniBand into a de facto proprietary ecosystem through vendor monopoly and closed optimizations. Here’s how that happened:
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- Vendor Monopoly: Nvidia is the sole manufacturer of AI-class InfiniBand silicon. Competitors like Intel abandoned the technology, while Broadcom and Cisco focus entirely on Ethernet.
- Proprietary Extensions: Nvidia injects closed-source hardware features like SHARP (which offloads AI math directly onto switches) that require a strict end-to-end Nvidia hardware pipeline.
- Software Lock-In: Management and orchestration tools are tightly bound to Nvidia’s proprietary CUDA and Unified Fabric Manager (UFM) stacks.
| Aspect | The Theoretical Standard | The Modern AI Reality |
|---|---|---|
| The Spec | Open, industry-standard managed by the IBTA. | Monopolized by a single vendor (Nvidia). |
| The Silicon | Anyone can build an InfiniBand chip. | Nvidia is the sole manufacturer of AI-class InfiniBand. |
| The Interconnect | Interoperable with various hardware platforms. | Tightly coupled with Nvidia GPUs and CUDA via proprietary extensions like SHARP. |
| Feature / Metric | Broadcom Open Ethernet Platform | Nvidia Proprietary InfiniBand Fabric |
|---|---|---|
| Architectural Philosophy | Open ecosystem. Decouples compute from networking to prevent vendor lock-in. | Vertically integrated. Tightly couples GPUs, switches, and software for a turn-key solution. |
| Top Raw Bandwidth | 102.4 Tbps single-chip switching capacity via Tomahawk 6. Supports native 800G per port. | 51.2 Tbps single-chip switching capacity on the latest Quantum-3 switches (400G per port). |
| Latency Profile | Average < 5µs using RoCE v2. Drops significantly via UEC 1.1 optimizations. | Native sub-2µs point-to-point latency with near-zero jitter. |
| Congestion & Reliability | Uses packet spraying, adaptive routing, and link-level retries via Ultra Ethernet Consortium (UEC). | Native credit-based flow control. Prevents buffer overflows at the hardware level for a completely lossless fabric. |
| Optical Integration | Leading the industry with Co-Packaged Optics (CPO) integrated onto the switch substrate. | Moving toward CPO integration in upcoming H2 2026 platform refreshes. |
| Relative Costs | Standard commoditized pricing. Roughly 1/3 the hardware cost of InfiniBand. | Premium pricing tied directly to Nvidia’s exclusive compute bundle. |
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References:
https://www.futuriom.com/articles/news/cisco-shows-full-stack-networking-strategy-at-ocp/2026/10
https://blogs.cisco.com/news/cisco-and-nvidia-announce-usfp-expanding-the-path-to-ai-connectivity
https://www.broadcom.com/company/news/resources/media-kits/2026-ocp-global-summit
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3 thoughts on “2026 OCP Summit: Full-Stack AI Networking Silicon from Nvidia/Cisco and Broadcom; Ethernet vs InfiniBand Interconnects”
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Oct 19, 2026 Update from Dell’Oro Group:
One of the biggest themes at OCP 2026 was the remarkable level of optical innovation and announcements—activity historically more associated with OFC. In my observation, the number of sessions dedicated to optics nearly doubled compared with last year.
This shift goes beyond the conference agenda. As AI networks demand more bandwidth, denser connectivity and increasingly distributed architectures, optics and switching silicon are becoming more tightly intertwined. Six developments stood out.
1. Co-Packaged Optics Moves Closer to Commercial Deployment
Co-packaged optics (CPO) reached an important milestone as NVIDIA moved its Spectrum-X Ethernet Photonics switches into production, with early customer adoption and deployments beginning. Celestica reinforced that momentum with its DS6005, a liquid-cooled 102.4 Tbps Ethernet switch based on Broadcom’s Tomahawk 6–Davisson CPO platform. It offers 64 × 1.6 Tbps ports in a compact 1.5OU form factor, using co-packaged optical engines and field-replaceable external lasers.
Near-packaged optics (NPO) also deserves attention. In its rack-scale architecture announcement, Arista identified open CPO/NPO alongside XPO as next-generation optical approaches for increasing network-rack density, citing a path from 1.6 Pb/s with current OSFP-based designs to 6.5 Pb/s per rack. This is an architectural density outlook—not evidence that NPO is already shipping in volume.
2. Pluggable Optics Fight Back with Higher Bandwidth Density
Even as CPO gains momentum, pluggable optics are far from standing still. NVIDIA and Cisco introduced plans for Ultra-Dense Small Form Factor Pluggable (USFP), a proposed 400 Gb/s-per-lane design with a path to as much as 12.8 Tbps of aggregate module capacity.
The companies are targeting four times the bandwidth density and approximately 1.3 times the power efficiency of 200 Gb/s-per-lane pluggable designs. That could connect more endpoints without adding network tiers while retaining familiar deployment flexibility and field serviceability. The story is not simply CPO versus pluggables: adoption will reflect density, power, reach, reliability, operating model and economics.
The significance is that optical integration is progressing from component roadmaps to complete systems and rack-level design choices. Customer qualification, serviceability, production yields and meaningful shipment volumes remain the metrics to watch. Early commercialization should not be confused with broad adoption.
3. The 100T Switch Era Is Here—and the Transition to 1.6T Is Underway
The 102.4 Tbps generation is taking shape across multiple silicon and systems ecosystems. Broadcom’s Tomahawk 6 underpins Arista’s 7060XE7 portfolio, which supports dense 1.6 Tbps connectivity with air- and liquid-cooled options. Celestica’s Tomahawk 6-based DS6000 and DS6001 are available to order, while the DS6005 extends the family into CPO.
Cisco’s OCP 2026 update reported initial customer shipments of G300-powered 102.4T systems and introduced the 51.2T Silicon One G302, with 200G SerDes and 1.6T connectivity for top-of-rack applications; G302 shipments were planned for before year-end 2026. NVIDIA is also advancing Spectrum-6, including Meta’s announced adoption for next-generation AI infrastructure.
The direction is clear: 100T-class switching and 1.6T ports are becoming building blocks of AI fabrics. But market readiness differs across announcements, orders, customer sampling and shipments. The next question is when 1.6T moves into a sustained volume ramp.
4. Scale-Up Is No Longer Confined to the Rack
One of the most consequential architectural disclosures during OCP was Microsoft’s Maia 300 scale-up domain, described as connecting 12,288 accelerators across 128 racks. It combines electrical links within racks with optical inter-rack connectivity and custom transport for accelerator-to-accelerator communication. The implication is that scale-up can be defined by workload communication requirements, not simply physical rack boundaries.
Additional announcements reinforce the breadth of this shift. Arista’s Etherlink SU-144 proposes open, Ethernet-based scale-up for as many as 144 accelerators in a single-hop domain and up to 1,024 across racks. Celestica and AMD’s Helios collaboration focuses on scale-up switches using Ultra Accelerator Link over Ethernet (UALoE) for AMD’s rack-scale AI platform. These are distinct architectures and development stages, but both point to Ethernet moving deeper into accelerator interconnects.
Meta’s Tahan scale-up switch offers another concrete example: a 51.2T, Broadcom Tomahawk 5-based Ethernet switch in the MTIA 300 system, using a lossless RoCE approach under FBOSS. Meta says Tahan is shipping and has outlined a future 72-accelerator-per-rack platform on 102.4T silicon, with a roadmap toward Ethernet for Scale-Up Networking (ESUN).
OpenAI and Broadcom’s Jalapeño announcement adds the accelerator-design perspective. Jalapeño is an inference-focused processor, not itself an Ethernet scale-up switch; nevertheless, its broader system platform incorporates Broadcom networking technologies, underscoring how chip architecture and fabric design are increasingly co-optimized.
Together, these developments challenge a hard rack boundary between scale-up and scale-out. They also create new opportunities for switching silicon, optics and open Ethernet fabrics, while raising questions around latency, transport semantics, congestion control and operational complexity.
5. Competition in Scale-Up Switching Silicon Is Heating Up
The emerging scale-up opportunity is drawing new suppliers and architectures. Upscale AI introduced its 115.2 Tbps SkyFabriX switching silicon as part of its standards-oriented Token Fabric portfolio. Astera Labs also unveiled its Orion rack-scale PCIe switching architecture, aimed at connecting multiple accelerators within a pod.
These announcements reinforce two trends: suppliers beyond incumbent networking-chip vendors are targeting the market, and no single interconnect is likely to fit every workload. Ethernet, PCIe, NVLink, UALink, and emerging open standards will be evaluated against bandwidth, latency, memory semantics, flexibility and cost. Scale-up is becoming a meaningful new battleground for silicon share.
6. Hyperscaler Customization and Open Networking Keep Advancing
Meta’s OCP 2026 networking disclosure illustrates a multi-vendor approach. Its IcePack liquid-cooled rack houses 102.4T IceCube scale-out switches offered in two silicon variants: Broadcom Tomahawk6C and NVIDIA Spectrum-6. Both use Meta’s FBOSS software and OCP Switch Abstraction Interface (SAI). NVIDIA separately detailed its Spectrum-6-based N-IceCube collaboration. Cisco Silicon One belongs in the broader open-switching competitive landscape at Meta, although Meta’s disclosed IceCube variants did not identify Cisco silicon. Arista’s earlier R4/HyperPort announcement provides another example of the scale-across dimension, although that product announcement preceded OCP 2026.
Cisco’s OCP announcement highlighted Silicon One deployments across hyperscale networks, including P200 systems in Microsoft and Alibaba environments. NVIDIA and Google also announced Falcon Transport support for future ConnectX-10 SuperNICs and BlueField DPUs, extending interoperability between transport software and networking hardware.
These examples show hyperscalers combining merchant silicon with their own software, protocols and system designs. Openness, multi sourcing and interoperability are strategic choices—not just implementation details—as AI factories grow larger and more specialized.
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If one message emerged from OCP 2026, it is that AI networking is no longer simply about faster switches. Optics, switching silicon and network architecture are co-evolving. CPO is entering early commercialization; NPO and other optical integration paths are gaining visibility; pluggables are pushing density higher; 100T systems and 1.6T connectivity are taking shape; and Ethernet scale-up is extending from the rack into larger accelerator domains.
Optics is no longer a supporting technology at the edge of the switching conversation. It is becoming an essential enabler of how the industry scales the next generation of AI infrastructure.
We provide deeper analysis of vendor positioning, customer wins, hyperscaler architectural choices and market adoption timelines, in our Data Center Switch—AI Back-end Networks reports. To access the reports, please contact us at [email protected].
https://www.delloro.com/ocp-2026-optics-takes-center-stage-in-enabling-the-next-wave-of-ai-networking-and-high-speed-switching/
From ChatGPT:
This is a strong addition to the original article. In particular, I like three aspects:
1. You distinguish early commercialization from broad market adoption. Your CPO discussion correctly emphasizes customer qualification, production yields, serviceability and shipment volumes—not just vendor announcements.
2. You expand the discussion beyond Ethernet versus InfiniBand. The Microsoft Maia 300 example, with 12,288 accelerators across 128 racks, illustrates how optical interconnects are changing the traditional boundaries between scale-up and scale-out.
3. You make optics central to the AI networking story. Your conclusion that optics is becoming an essential enabler of AI infrastructure is particularly important. CPO, NPO and higher-density pluggable optics are competing and complementary approaches, not simply successive replacements.
I especially like this sentence:
“The story is not simply CPO versus pluggables: adoption will reflect density, power, reach, reliability, operating model and economics.”
That’s an excellent way to frame the market.
In summary, your October 24th IEEE update comment from Dell’Oro Group arguably adds more market and architectural insight than the original vendor-focused coverage. It moves the discussion from announcements to actual deployment maturity and the economics of scaling AI networks. I think IEEE Techblog readers will appreciate that distinction.
From ChatGPT which was NOT used in any way to research or write this article:
The most important takeaway from OCP 2026 is that AI networking is becoming a system-level competition, not simply a contest over switch bandwidth. NVIDIA’s tightly integrated InfiniBand and Ethernet platforms offer performance and operational advantages, while Broadcom, Cisco and other suppliers are advancing more open, multi-vendor Ethernet alternatives. But openness alone does not guarantee lower cost or better performance. The real test will be end-to-end workload efficiency—including latency, congestion management, power consumption, reliability and the software required to operate very large accelerator clusters.
As AI infrastructure scales, networking architecture and optical technology will increasingly determine the economics of AI computing, not just the performance of the accelerators themselves.